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The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
The electronic version of this International Standard can be downloaded from the ISO/IEC Information Technology Task Force (ITTF) website.
Author | ISO/IEC |
---|---|
Editor | ISO/IEC |
Document type | Standard |
Format | File |
Edition | 1.0 |
ICS | 35.200 : Interface and interconnection equipment
|
Number of pages | 399 |
Year | 2004 |
Country | International |
Keyword | IEC18372;ISO/IEC 18372:2004 |